1. Field of the Invention
The present invention relates to a method of fabricating source and drain contacts and a channel region.
Also, the present invention relates to a FET comprising such source and drain contacts and such a channel region. Furthermore, the present invention relates to a semiconductor device comprising such a FET.
2. Description of the Related Art
U.S. Pat. No. 6,458,662 B1 discloses a method of fabricating a dual gate MOSFET. The method defines an asymmetrical dual gate structure which flanks a fin structure and is disposed approximately 90° from the source/drain structure in the Si layer. The fin structure comprises an epitaxial SiGe/Si/SiGe sandwich which acts as a channel region.
After the formation of the fin structure and the gate electrodes, the source and drain regions are formed in a completing step.
Such a Double-Gate structure from the prior art has certain disadvantages.
Due to its layout the double gate structure has a current path which substantially resides in the sidewalls of the fin. This type of current path may result in a deterioration of the performance of the device unless extreme care is taken to ensure that a substantially perfect interface exists between the Si region, the side-walls and the dielectric region(s).
Also, depending on the orientation of the fin on the wafer, the current path lies in different crystallographic planes of Si, resulting in a different current drivability.
Moreover, the formation of the source/drain junctions may be complicated by the fact that high-angle implantations of dopants have to be used to reach the whole volume of the respective fin parts.
Furthermore, the height of the fin sets the absolute value of the current drive of the device (here the height acts similarly as a “width” dimension of a conventional MOSFET). Typically, in modern circuits the aspect ratio of the gate length to the width is as large as 10 (or even 20 for P-type devices), which means that for a gate length of 50 nm, the height of the fin would have to be about 500 nm.
At the same time the fin width (Si channel thickness between the gates) has to be smaller than ⅓ of the gate length, which for a 50 nm gate device of this example would imply a fin width of 16.5 nm. As is known to persons skilled in the art, the formation of the fin having a width of about 16 nm and a height of about 500 nm is not possible with current manufacturing capabilities (an aspect ratio between fin width and device height up to 5-6 seems reasonable, but a ratio of about 30 as described above in this example is not). A solution for this problem is believed to be the use of multiple fins for a device, however, this requires some significant issues to be resolved: all fins have to be exactly the same, and they cannot be spaced densely since the formation of source/drain junctions as mentioned above requires sufficient distance to allow high-angle implantations to be performed.
In summary, the combination of all the factors mentioned above results in a very important limitation of the prior art. This limitation necessitates that most of the current circuit designs must be re-done completely. Ideally, one would want to have a multi-gate device which, at least from the point of view of a circuit designer, is exactly the same as a standard planar single gate device.
This implies that a planar device, with the Si channel sandwiched in between two gates, would be much more suitable. However, in fabricating such a double-gate device, there are two major issues that have to be overcome:                alignment of the two gates to each other (if not, parasitic capacitances will have a serious effect on the speed of operation of the device),        source/drain contacts are required to have the lowest possible resistance (otherwise the current drive will be significantly reduced) and a very steep/sharp interface to the channel (otherwise the short-channel effects will be pronounced).        